Typically, silicon devices operate in response to a clock signal. Clock signals are used to transfer data and otherwise provide timing signals for operation of processing devices.
It may be necessary to use more than one clock signal on a chip, since various tasks performed by the chip may require different clock rates. These different clock rates are referred to as clock domains. Difficulties may be encountered in the transfer of data from one clock domain to another clock domain on a chip.
Latency in data transfers is the delay that is created in transferring data through a system. Latency can adversely affect data processing in computer systems by delaying the transfer of data and creating problems associated with reading and writing of data. It is therefore advantageous to eliminate latency, wherever possible, to increase the speed at which systems operate and minimize other problems associated with latency.
The process of transferring data from one clock domain to another clock domain in a FIFO may add a significant amount of latency to the overall transfer. This latency is the result of the processes that are necessary to ensure that the FIFO is not overflowed or underflowed during the transfer process.